Recently, the main issue of semiconductor memory devices is shifted from a degree of integration to an operating speed. Accordingly, high-speed synchronous DRAMs such as a DDR SDRAM (Double Data Rate Synchronous DRAM) and a RAMBUS DRAM are focused on high-speed data processing units.
The high-speed synchronous DRAMs are memory devices in which data are processed in synchronization with an external clock signal and this operation mechanism is a mainstream approach in the mass production of DRAM devices. The accesses for data input/output operation of the SDRAMs are carried out periodically in synchronization with a rising edge of an external clock signal. However, in the DDR SDRAM, the data input/output operation are periodically carried out twice in synchronization with rising and falling edges, respectively, of the external clock signal using an internal DLL (Delay Locked Loop) circuit. That is, the DDR SDRAM is twice as fast as the SDRAM. Therefore, a high-speed semiconductor memory device such as the DDR SDRAM produces a clock signal (hereinafter, referred to as “rising clock signal rclk”) which is enabled in response  to a rising edge time of the external clock signal and another clock signal (hereinafter, referred to as “falling clock signal fclk”) which is enabled in response to a falling edge time of the external clock signal.
FIG. 1 is a circuit diagram illustrating a clock signal generating circuit by the conventional technology.
Referring to FIG. 1, the clock signal generating circuit of a conventional DDR SDRAM includes first and second clock signal generators 100 and 110. The first clock signal generator 100 includes a pair of inverters IV11 and IV12 for buffering an external clock signal ECLK, a delayer 101 for delaying an output signal of a node nd11 for a predetermine time, an inverter IV13 for inverting an output signal of the delayer 101, a logic circuit having a NAND gate ND11 for performing a NAND operation of the output signal of the node nd11 and an output signal of the inverter IV13, and an inverter IV14. The second clock signal generator 110 includes a transfer gate T11 for transferring the external clock signal ECLK, an inverter IV15 for inverting an output signal of the transfer gate T11, a delayer 111 for delaying an output signal of a node nd12 for a predetermine time, an inverter IV16 for inverting an output signal of the delayer 111, and a logic circuit having a NAND gate ND12 for performing a NAND operation of the output signal of the node nd12 and an output signal of the inverter IV16, and an inverter IV17
This configured clock signal generating circuit produces both a rising clock signal rclk having a predetermined pulse width in synchronization with a rising edge of the external clock signal ECLK and a falling clock signal fclk having a predetermined pulse width in  synchronization with a falling edge of the external clock signal ECLK. At a read operation, data are outputted in synchronization with the rising clock signal rclk as well as the falling clock signal fclk.
However, the rising and falling clock signals rclk and fclk of the conventional clock signal generating circuit can be outputted faster or later under the influence of PVT (Process, Voltage and Temperature) fluctuation. For instance, as shown in FIG. 2, in a case that a MOS transistor has a fast operating characteristic according to a manufacturing process, data which are issued in synchronization with the rising and falling clock signal rclk and fclk can be outputted faster than a predetermined data output section (more particularly, second rising edge of the external clock signal ECLK).